The present invention is related to the testing of integrated circuits and, more particularly, to the testing of integrated circuits with minimum intrusion to integrated circuit designs and minimal impact on times to perform test procedures on the integrated circuits.
Since the first integrated circuit in the late 1950's, the number of transistors and wiring interconnects on a single chip has increased dramatically. Today, hundreds of millions of transistors and wiring interconnections may be found in one integrated circuit. With this increased complexity has come problems in testing the functional integrity of integrated circuits.
There are many approaches to integrated circuit testing. One approach is the use of test equipment, such as a chip tester, which initiates a sequence of digital events on the input pins of the integrated circuit and on a triggering event records the signals on the output pins of the integrated circuit for external analysis by the logic analyzer. However, this traditional approach requires the integrated circuit to be operational and signals to travel through the integrated circuit's input/output blocks to the external world. The internal workings of the integrated circuit is tested only through the device's input/output interfaces. Another approach is to build test circuits in the integrated circuit itself in order to directly test selected internal nodes of the integrated circuit. For such testing, the integrated circuit is generally operated in a test mode. For example, using test methodologies, such as IEEE 1449.1 (commonly referred to as JTAG), test vectors are scanned into the integrated circuit to set the states of internal nodes and then the test results are retrieved from the integrated circuit.
Whatever approach is taken to test the integrated circuit, it is desirable that not only the testing be effective, but that the amount of circuit resources and time dedicated to testing be minimized. If test circuits are built on the integrated circuit, they should not consume too much space on the substrate. Preferably, as much as possible of the substrate should be dedicated to original purpose of the integrated circuit. Furthermore, the added test circuits should avoid or minimize any increase in the time for testing the integrated circuits.
The present invention provides for such testing in an integrated circuit, particularly certain integrated circuits with multiple sources for output pins.